PSD4211F3V-70UI 查看數據表（PDF） - STMicroelectronics
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PSD4211F3V-70UI
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PSD4211F3V-70UI Datasheet PDF : 89 Pages
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PSD4235G2
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 16-bit MCUs, with their
bus types and control signals, are shown in Table
34. The MCU interface type is specified using the
PSDsoft Express.
PSD Interface to a Multiplexed Bus. Figure 19
shows an example of a system using a MCU with
a 16-bit multiplexed bus and a PSD4235G2. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port E, F
or G. The PSD drives the ADIO data bus only
when one of its internal resources is accessed and
Read Strobe (RD, CNTL1) is active. Should the
system address bus exceed sixteen bits, Ports A,
B, C, or F may be used as additional address in-
puts.
PSD Interface to a Non-Multiplexed 8-Bit Bus.
Figure 20 shows an example of a system using a
MCU with a 16-bit non-multiplexed bus and a
PSD4235G2. The address bus is connected to the
ADIO Port, and the data bus is connected to Ports
F and G. Ports F and G are in tri-state mode when
the PSD is not accessed by the MCU. Should the
system address bus exceed sixteen bits, Ports A,
B, or C may be used for additional address inputs.
Table 34. MCUs and their Control Signals
MCU
CNTL0 CNTL1 CNTL2
PD3
PD02
ADIO0 PF3-PF0
68302, 68306, MMC2001
R/W
LDS
UDS
(Note 1) AS
—
(Note 1)
68330, 68331, 68332, 68340 R/W
DS
SIZ0
(Note 1) AS
A0
(Note 1)
68LC302, MMC2001
WEL
OE
—
WEH
AS
—
(Note 1)
68HC16
R/W
DS
SIZ0
(Note 1) AS
A0
(Note 1)
68HC912
R/W
E
LSTRB DBE
E
A0
(Note 1)
68HC812 3
R/W
E
LSTRB (Note 1) (Note 1) A0
(Note 1)
80196
WR
RD
BHE
(Note 1) ALE
A0
(Note 1)
80196SP
WRL
RD
(Note 1) WRH
ALE
A0
(Note 1)
80186
WR
RD
BHE
(Note 1) ALE
A0
(Note 1)
80C161, 80C164-80C167
WR
RD
BHE
(Note 1) ALE
A0
(Note 1)
80C51XA
WRL
RD
PSEN
WRH
ALE
A4/D0
A3-A1
H8/300
WRL
RD
(Note 1) WRH
AS
A0
—
M37702M2
R/W
E
BHE
(Note 1) ALE
A0
(Note 1)
Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O func-
tions.
2. ALE/AS input is optional for MCUs with a non-multiplexed bus
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