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STM32F301R6Y6TR 查看數據表(PDF) - STMicroelectronics

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STM32F301R6Y6TR Datasheet PDF : 135 Pages
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Electrical characteristics
STM32F301x6 STM32F301x8
6.3.19 DAC electrical specifications
Table 69. DAC characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
VDDA Analog supply voltage DAC output buffer ON
2.4
RLOAD(1) Resistive load
DAC output buffer ON Connected to VSSA
5
Connected to VDDA
25
RO(1) Output impedance DAC output buffer ON
-
CLOAD(1) Capacitive load
DAC output buffer ON
-
Corresponds to 12-bit input code (0x0E0) to
(0xF1C) at VDDA = 3.6 V
VDA(C1_) OUT
Voltage on DAC_OUT and (0x155) and (0xEAB) at VDDA = 2.4 V
output
DAC output buffer ON.
0.2
DAC output buffer OFF
-
IDDA(3)
DNL(3)
DAC DC current
consumption in
quiescent mode
(Standby mode)(2)
Differential non
linearity Difference
between two
consecutive code-
1LSB)
With no load, middle code (0x800) on the
input.
-
With no load, worst code (0xF1C) on the input. -
Given for a 10-bit input code
-
Given for a 12-bit input code
-
-
3.6
V
-
-
kΩ
-
-
-
15
kΩ
-
50
pF
- VDDA – 0.2 V
0.5
VDDA -
1LSB
mV
-
380
µA
-
480
µA
-
±0.5 LSB
-
±2
LSB
INL(3)
Integral non linearity Given for a 10-bit input code
(difference between
measured value at
Code i and the value
at Code i on a line Given for a 12-bit input code
drawn between Code
0 and last Code 4095)
-
-
-
-
Offset error (difference
-
-
-
Offset(3)
between measured
value at Code (0x800)
Given for a 10-bit input code at VDDA = 3.6 V
-
-
and the ideal value =
VDDA/2)
Given for a 12-bit input code at VDDA = 3.6 V
-
-
Gain error(3) Gain error
Given for a 12-bit input code
-
-
Settling time (full
scale: for a 12-bit input
code transition
tSETTLING(3) between the lowest
and the highest input
CLOAD 50 pF,
RLOAD 5 kΩ
codes when
DAC_OUT reaches
-
3
±1
LSB
±4
LSB
±10
mV
±3
LSB
±12 LSB
±0.5
%
4
µs
108/135
DocID025146 Rev 6

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