PIC32MX250F128C-I/SO 查看數據表（PDF） - Microchip Technology

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PIC32MX250F128C-I/SO

32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX

REGISTER 16-1: SPIxCON: SPI CONTROL REGISTER

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

31:24

23:16

15:8

7:0

R/W-0

R/W-0

FRMEN FRMSYNC

R/W-0

U-0

MCLKSEL(2)

—

R/W-0

U-0

ON(1)

—

R/W-0

R/W-0

SSEN

CKP

R/W-0

FRMPOL

U-0

—

R/W-0

SIDL

R/W-0

MSTEN

R/W-0

MSSEN

U-0

—

R/W-0

DISSDO

R/W-0

DISSDI

R/W-0

R/W-0

R/W-0

R/W-0

FRMSYPW

FRMCNT<2:0>

U-0

U-0

R/W-0

R/W-0

—

—

SPIFE ENHBUF(2)

R/W-0

MODE32

R/W-0

MODE16

R/W-0

SMP

R/W-0

CKE(3)

R/W-0

R/W-0

R/W-0

R/W-0

STXISEL<1:0>

SRXISEL<1:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31

FRMEN: Framed SPI Support bit

1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)

0 = Framed SPI support is disabled

bit 30

FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)

1 = Frame sync pulse input (Slave mode)

0 = Frame sync pulse output (Master mode)

bit 29

FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)

1 = Frame pulse is active-high

0 = Frame pulse is active-low

bit 28

MSSEN: Master Mode Slave Select Enable bit

1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in

Master mode. Polarity is determined by the FRMPOL bit.

0 = Slave select SPI support is disabled.

bit 27

FRMSYPW: Frame Sync Pulse Width bit

1 = Frame sync pulse is one character wide

0 = Frame sync pulse is one clock wide

bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per

pulse. This bit is only valid in FRAMED_SYNC mode.

111 = Reserved; do not use

110 = Reserved; do not use

101 = Generate a frame sync pulse on every 32 data characters

100 = Generate a frame sync pulse on every 16 data characters

011 = Generate a frame sync pulse on every 8 data characters

010 = Generate a frame sync pulse on every 4 data characters

001 = Generate a frame sync pulse on every 2 data characters

000 = Generate a frame sync pulse on every data character

bit 23 MCLKSEL: Master Clock Enable bit(2)

1 = REFCLK is used by the Baud Rate Generator

0 = PBCLK is used by the Baud Rate Generator

bit 22-18 Unimplemented: Read as ‘0’

bit 17

SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)

1 = Frame synchronization pulse coincides with the first bit clock

0 = Frame synchronization pulse precedes the first bit clock

Note 1:

2:

3:

When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in

the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

This bit can only be written when the ON bit = 0.

This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

DS61168C-page 166

Preliminary

© 2011 Microchip Technology Inc.

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