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PIC32MX250F128C-I/SO 查看數據表(PDF) - Microchip Technology

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PIC32MX250F128C-I/SO Datasheet PDF : 321 Pages
First Prev 161 162 163 164 165 166 167 168 169 170 Next Last
PIC32MX1XX/2XX
REGISTER 16-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)
bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
Note 1:
2:
3:
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit can only be written when the ON bit = 0.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
DS61168C-page 168
Preliminary
© 2011 Microchip Technology Inc.

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