STM32F302xx/STM32F303xx
Electrical characteristics
6.3.18
ADC characteristics
Unless otherwise specified, the parameters given in Table 66 to Table 69 are guaranteed by
design, with conditions summarized in Table 22.
Table 66. ADC characteristics
Symbol
Parameter
VDDA
Analog supply voltage for
ADC
fADC ADC clock frequency
fS(1) Sampling rate
fTRIG(1) External trigger frequency
VAIN
RAIN(1)
CADC(1)
Conversion voltage range
External input impedance
Internal sample and hold
capacitor
tCAL(1) Calibration time
tlatr(1)
Trigger conversion latency
Regular and injected
channels without conversion
abort
tlatrinj(1)
Trigger conversion latency
Injected channels aborting a
regular conversion
tS(1) Sampling time
TADCVREG ADC Voltage Regulator
(1)
_STUP
Start-up time
tCONV(1)
Total conversion time
(including sampling time)
1. Data guaranteed by design
Conditions
Resolution = 12 bits,
Fast Channel
Resolution = 10 bits,
Fast Channel
Resolution = 8 bits,
Fast Channel
Resolution = 6 bits,
Fast Channel
fADC = 72 MHz
Resolution = 12 bits
Resolution = 12 bits
fADC = 72 MHz
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
fADC = 72 MHz
fADC = 72 MHz
Resolution = 12 bits
Resolution = 12 bits
Min
Typ Max Unit
2
-
3.6
V
0.14
-
72
MHz
0.01
-
5.14
0.012
0.014
-
6
MSPS
-
7.2
0.0175
-
9
-
-
-
-
0
-
-
-
-
5
1.5
-
-
-
2.5
-
-
-
0.021
1.5
1.56
112
2
-
-
-
3
-
-
-
-
-
-
-
5.14 MHz
14
VDDA
100
1/fADC
V
kΩ
-
pF
2.5
2
2.25
2.125
3.5
3
3.25
3.125
8.35
601.5
10
µs
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
µs
1/fADC
µs
0.19
-
3.5
µs
14 to 252 (tS for sampling + 12.5 for
successive approximation)
1/fADC
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