ST72F324J2TCRS 查看數據表（PDF） - STMicroelectronics

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ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

10.5.4 Functional description

The block diagram of the serial control interface is shown in Figure 55. It contains six

dedicated registers:

● 2 control registers (SCICR1 and SCICR2)

● a status register (SCISR)

● a baud rate register (SCIBRR)

● an extended prescaler receiver register (SCIERPR)

● an extended prescaler transmitter register (SCIETPR)

Refer to the register descriptions in Section 10.5.7 for the definitions of each bit.

Serial data format

t(s) Word length may be selected as being either 8 or 9 bits by programming the M bit in the

SCICR1 register (see Figure 55).

uc The TDO pin is in low state during the start bit.

rod The TDO pin is in high state during the stop bit.

P An Idle character is interpreted as an entire frame of ‘1’s followed by the start bit of the next

frame which contains data.

lete A Break character is interpreted on receiving ‘0’s for some multiple of the frame period. At

o the end of the last break frame the transmitter inserts an extra ‘1’ bit to acknowledge the

s start bit.

b Transmission and reception are driven by their own baud rate generator.

) - O Figure 56. Word length programming

t(s 9-bit word length (M bit is set)

uc Data frame

Possible

Parity

Next data frame

d bit

Next

roStart

bit

bit 0

bit 1 bit 2

bit 3

bit 4 bit 5

bit 6

bit 7 bit 8

Stop

bit

Start

bit

te P Idle frame

Start

bit

ole Break frame

Obs 8-bit word length (M bit is reset)

Extra

’1’

Start

bit

Data frame

Possible

Next data frame

Parity

bit

Next

Start

bit

bit 0

bit 1 bit 2

bit 3

bit 4 bit 5

bit 6

bit 7

Stop

Bit

Start

bit

Idle frame

Start

bit

Break frame

Extra

’1’

Start

bit

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Doc ID 13841 Rev 1

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