ST72F324J2TCRS 查看數據表（PDF） - STMicroelectronics

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ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

Break characters

Setting the SBK bit loads the shift register with a break character. The break frame length

depends on the M bit (see Figure 56).

As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this

bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the

recognition of the start bit of the next frame.

Idle characters

Setting the TE bit drives the SCI to send an idle frame before the first data frame.

Clearing and then setting the TE bit during a transmission sends an idle frame after the

current word.

Obsolete Product(s) - Obsolete Product(s) Note:

Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore,

the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next

byte in the SCIDR.

Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9

bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this

mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the

received shift register (see Figure 55).

Procedure

1. Select the M bit to define the word length.

2. Select the desired baud rate using the SCIBRR and the SCIERPR registers.

3. Set the RE bit, this enables the receiver which begins searching for a start bit.

When a character is received:

● The RDRF bit is set. It indicates that the content of the shift register is transferred to the

RDR.

● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.

● The error flags can be set if a frame error, noise or an overrun error has been detected

during reception.

Clearing the RDRF bit is performed by the following software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register.

The RDRF bit must be cleared before the end of the reception of the next character to avoid

an overrun error.

Break character

When a break character is received, the SCI handles it as a framing error.

Idle character

When a idle frame is detected, there is the same procedure as a data received character

plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.

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Doc ID 13841 Rev 1

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