ST72F324J2TCRS 查看數據表（PDF） - STMicroelectronics
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ST72F324J2TCRS
STMicroelectronics
ST72F324J2TCRS Datasheet PDF : 194 Pages
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On-chip peripherals
ST72324xx-Auto
Table 63. SCICR1 register description (continued)
Bit Name
Function
Wake-Up method
3 WAKE
This bit determines the SCI Wake-Up method, it is set or cleared by software.
0: Idle line
1: Address mark
Parity Control Enable
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th bit
2 PCE
if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
) 1: Parity control enabled
t(s Parity Selection
Produc 1 PS
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be selected
after the current byte.
0: Even parity
1: Odd parity
te Parity Interrupt Enable
bsole 0 PIE
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
t(s) - O SCI Control Register 2 (SCICR2)
uc SCICR2
Reset value: 0000 0000 (00h)
d 7
6
5
4
3
2
1
0
Pro TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
teR/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
soleTable 64. SCICR2 register description
Ob Bit Name
Function
Transmitter Interrupt Enable
7 TIE
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
Transmission Complete Interrupt Enable
6 TCIE
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
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Doc ID 13841 Rev 1
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