ST72F324J2TCRS 查看數據表（PDF） - STMicroelectronics

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ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

Table 64. SCICR2 register description (continued)

Bit Name

Function

Receiver interrupt Enable

5 RIE

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR

register.

Idle Line Interrupt Enable

4 ILIE

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.

Transmitter Enable

te Product(s) 3 TE

This bit enables the transmitter. It is set and cleared by software.

0: Transmitter is disabled

1: Transmitter is enabled

Notes:

- During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble

(Idle line) after the current word.

- When TE is set there is a 1 bit-time delay before the transmission starts.

Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits

are both cleared (or if TE is never set).

le Receiver Enable

t(s) - Obso 2 RE

This bit enables the receiver. It is set and cleared by software.

0: Receiver is disabled

1: Receiver is enabled and begins searching for a start bit

Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive

some data, otherwise it cannot function in Mute mode with Wake-Up by Idle line

detection.

Receiver Wake-Up

roduc 1 RWU

This bit determines if the SCI is in mute mode or not. It is set and cleared by

software and can be cleared by hardware when a wake-up sequence is recognized.

0: Receiver in Active mode

1: Receiver in Mute mode

te P Send Break

Obsole0 SBK

This bit set is used to send break characters. It is set and cleared by software.

0: No break character is transmitted.

1: Break characters are transmitted.

Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter will send a Break word

at the end of the current word.

SCI Data Register (SCIDR)

This register contains the received or transmitted data character, depending on whether it is

read from or written to.

SCIDR

Reset value: undefined

7

6

5

4

3

2

1

0

Doc ID 13841 Rev 1

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