ST72F324J2TCRE 查看數據表（PDF） - STMicroelectronics

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ST72F324J2TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

Interrupts

7.6

External interrupts

7.6.1 I/O port interrupt sensitivity

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR

register (Figure 20). This control allows up to four fully independent external interrupt source

sensitivities.

Each external interrupt source can be generated on four (or five) different events on the pin:

● Falling edge

● Rising edge

● Falling and rising edge

● Falling edge and low level

t(s) ● Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified

uc only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that

d interrupts must be disabled before changing sensitivity.

ro The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits

P of the EICR.

lete Figure 20. External interrupt control bits

so Port A3 interrupt

Ob PAOR.3

PADDR.3

- PA3

t(s) IPA BIT

c Port F [2:0] interrupts

du PFOR.2

roPFDDR.2

PPF2

EICR

IS20 IS21

Sensitivity

control

EICR

IS20 IS21

Sensitivity

PF2

control

PF1

PF0

ei0 interrupt source

ei1 interrupt source

olete Port B [3:0] interrupts

bs PBOR.3

PBDDR.3

O PB3

EICR

IS10 IS11

Sensitivity

PB3

control

PB2

ei2 interrupt source

PB1

PB0

IPB BIT

Port B4 interrupt

PBOR.4

PBDDR.4

PB4

EICR

IS10 IS11

Sensitivity

control

ei3 interrupt source

Doc ID 13841 Rev 1

49/193

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