ST72F324J2TCRE 查看數據表（PDF） - STMicroelectronics

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ST72F324J2TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

Figure 26. HALT timing overview

Power saving modes

256 or 4096 CPU

Run Halt

cycle delay

Run

Halt

instruction

[MCCSR.OIE = 0]

Reset

or

interrupt

Fetch

vector

Figure 27. Halt mode flowchart

t(s) Halt instruction

(MCCSR.OIE = 0)

uc Enable

Watchdog

rod WDGHALT(1)

0

Disable

P 1

te Watchdog

ole reset

Oscillator

off

Peripherals(2)

off

CPU

off

I[1:0] bits

10

ObsN

Reset

) - N

Y

t(s Interrupt(3)

cY

Oscillator

on

Peripherals

off

u CPU

d I[1:0] bits

on

XX(4)

Pro 256 or 4096 CPU clock

cycle delay

lete Oscillator

Peripherals

o CPU

s I[1:0] bits

on

on

on

XX(4)

Ob Fetch reset vector

or service interrupt

1. WDGHALT is an option bit. See Section 14.1: Flash device configuration on page 178 for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 25: Interrupt mapping for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is

popped.

Doc ID 13841 Rev 1

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