ST72F324K2TCTRS 查看數據表（PDF） - STMicroelectronics

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ST72F324K2TCTRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

One Pulse mode

One Pulse mode enables the generation of a pulse when an external event occurs. This

mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure

To use One Pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the

formula below).

2. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the

pulse.

t(s) – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the

pulse.

uc – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

d ICAP1 pin must be configured as floating input).

ro 3. Select the following in the CR2 register:

P – Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1

te function.

le – Set the OPM bit.

o – Select the timer clock CC[1:0] (see Table 50).

bs Figure 44. One pulse mode cycle

t(s) - O When

event occurs

c on ICAP1

rodu When

P counter =

OC1R

ICR1 = Counter

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

OCMP1 = OLVL1

oleteThen, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is

bs loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R

O register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the

ICIE bit is set.

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two

steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Doc ID 13841 Rev 1

85/193

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