ST72F324K2TCTRS 查看數據表（PDF） - STMicroelectronics

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ST72F324K2TCTRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

10.3.6 Summary of timer modes

Table 48. Summary of timer modes

Mode

Input

Capture 1

Timer resources

Input

Capture 2

Output

Compare 1

Output

Compare 2

Input Capture

(1 and/or 2)

Yes

Output Compare

(1 and/or 2)

Yes(1)(2)

Yes(2)

Yes

Yes(3)

One Pulse mode

t(s) No

c PWM mode

Not

recommended(2)(4)

No

Not

recommended(2)(5)

Partially(1)

No

du 1. See Note 5 and Note 6 in One Pulse mode on page 85.

ro 2. In Flash devices, Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0.

P 3. In Flash devices, the TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2 event

cannot be generated, OCF2 is forced by hardware to 0.

te 4. See Note 4 in One Pulse mode on page 85.

le 5. See Note 4 in Pulse Width Modulation mode on page 87.

uct(s) - Obso 10.3.7

16-bit timer registers

Each timer is associated with 3 control and status registers, and with 6 pairs of data

registers (16-bit values) relating to the 2 input captures, the 2 output compares, the counter

and the alternate counter.

Control Register 1 (CR1)

rod CR1

P7

leteICIE

Obso R/W

6

OCIE

R/W

5

TOIE

R/W

4

FOLV2

R/W

3

FOLV1

R/W

Reset value: 0000 0000 (00h)

2

1

0

OLVL2

IEDG1

OLVL1

R/W

R/W

R/W

M

Table 49. CR1 register description

Bit Name

Function

Input Capture Interrupt Enable

7 ICIE

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is

set.

Output Compare Interrupt Enable

6 OCIE

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register

is set.

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Doc ID 13841 Rev 1

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