CDB8952T-IQ 查看數據表（PDF） - Cirrus Logic

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CDB8952T-IQ

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Cirrus Logic 

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60.

These three-level pins allow adjustment to the rise and fall times of the 100BASE-TX

transmitter output waveform. The rise and fall times are symmetric.

TXSLEW0 pin

low

low

low

floating

floating

floating

high

high

high

TXSLEW1 mode

low

floating

high

low

floating

high

low

floating

high

Rise/Fall time

0.5 ns

1.0 ns

1.5 ns

2.0 ns

2.5 ns

3.0 ns

3.5 ns

4.0 ns

4.5 ns

Media Interface Pins

RX+, RX- - 10/100 Receive. Differential Input Pair, Pins 91 and 92.

Differential input pair receives 10 or 100 Mb/s data from the receive port of the transformer

primary.

TX+, TX- - 10/100 Transmit. Differential Output Pair, Pins 80 and 81.

Differential output pair drives 10 or 100 Mb/s data to the transmit port of the transformer

primary.

General Pins

CLK25 - 25 MHz Clock. Tristate Output, Pin 17.

A 25 MHz Clock is output on this pin when the CS8952T is configured to use an external

reference transmit clock in TX_CLK IN MASTER mode. See the pin description for the

Transmit Clock Mode Initialization pin (TCM) for more information on TX_CLK operating

modes.

CLK25 may also be enabled regardless of the TCM pin state by clearing bit 7 of the PCS Sub-

layer Configuration Register (address 17h).

RES - Reference Resistor. Input, Pin 86.

This input should be connected to ground with a 4.99 kΩ +/-1% series resistor. The resistor is

needed for the biasing of internal analog circuits.

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

DS206TPP2

15

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