CDB8952T-IQ 查看數據表（PDF） - Cirrus Logic

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CDB8952T-IQ

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Cirrus Logic 

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

spurious carrier activity from propagating through

the repeater to other attached segments.

The false carrier detection logic described earlier is

used to increment a false carrier counter. When two

consecutive false carrier events are detected, the

CS8952T will deassert the Link OK bit in the Self

Status Register (address 19h), set the Link Status

Change bit in the Interrupt Status Register (address

11h), increment the Disconnect Count Register

(address 12h), stop propagating received data to the

MII, and ignore any transmit data from the MII.

The receiver will continue to monitor the received

data stream for valid IDLE symbols. Once dis-

abled, the receiver and transmitter will remain dis-

abled until the Link Integrity Monitor has

determined the link has again stabilized.

The Carrier Integrity Monitor may be disabled

through the CIM Disable bit in the PCS Sub-Layer

Configuration Register (address 17h). It is enabled

by default when the REPEATER pin is asserted on

reset or power-up.

10BASE-T MII Application

The digital interface used in this mode is the same

as that used in the 100BASE-X nibble modes ex-

cept that TX_CLK and RX_CLK are nominally

2.5 MHz.

The CS8952T includes a full-featured 10BASE-T

interface, as described in the following sections.

Duplex operation

The CS8952T supports both 10BASE-T full and

half duplex operation as determined by pins

AN[1:0] and/or the corresponding MII register bits.

(See Table 5 on page 23).

Carrier Detection

The carrier detect circuit informs the MAC that

valid receive data is present by asserting the Carrier

Sense signal (CRS) as soon it detects a valid bit

pattern (1010b or 0101b for 10BASE-T). During

normal packet reception, CRS remains asserted

while the frame is being received, and is de-assert-

ed within 2.3 bit times after the last low-to-high

transition of the End-of-Frame (EOF) sequence.

Whenever the receiver is idle (no receive activity),

CRS is de-asserted.

Collision Detection

If half duplex operation is selected, the CS8952T

detects a 10BASE-T collision whenever the receiv-

er and transmitter are active simultaneously. When

a collision is present, the collision is reported on

pin COL.

Collision detection is undefined for full-duplex op-

eration.

Jabber

The jabber timer monitors the transmitter and dis-

ables the transmission if the transmitter is active for

greater than approximately 105 ms. The transmit-

ter stays disabled until approximately 406 ms after

the internal transmit request is no longer enabled.

Link Test Pulses

To prevent disruption of network operation due to

a faulty link segment, the CS8952T continually

monitors the 10BASE-T receive pair (RXD+ and

RXD-) for packets and link pulses. After each

packet or link pulse is received, an internal Link-

Loss timer is started. As long as a packet or link

pulse is received before the Link-Loss timer finish-

es (between 50 and 100 ms), the CS8952T main-

tains normal operation. If no receive activity is

detected, the CS8952T disables packet transmis-

sion to prevent “blind” transmissions onto the net-

work (link pulses are still sent while packet

transmission is disabled). To reactivate transmis-

sion, the receiver must detect a single packet (the

packet itself is ignored), or two normal link pulses

separated by more than 6 ms and no more than

50 ms.

In the absence of transmit packets, the transmitter

generates link pulses in accordance with

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

DS206TPP2

21

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