CDB8952T-IQ 查看數據表（PDF） - Cirrus Logic
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CDB8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Basic Mode Control Register - Address 00h
15
Software
Reset
14
Loopback
13
Speed
Selection
12
Auto-Neg
Enable
7
6
5
4
Collision Test
11
Power Down
3
Reserved
10
Isolate
2
9
Restart
Auto-Neg
8
Duplex Mode
1
0
BIT
NAME
15 Software Reset
TYPE
Read/Set 0
RESET
DESCRIPTION
Setting this bit performs a chip-wide reset. All status
and control registers are set to their default states,
and the analog circuitry is re-calibrated. This bit is an
Act-Once bit which is cleared once the reset and re-
calibration have completed.
14 Loopback
Read/Write 0
This bit will also be set automatically while the analog
circuitry is reset and re-calibrated during mode
changes.
When set, the CS8952T is placed in a loop back
mode. Any data sent on the transmit data path is
returned on the receive data path. Loopback mode is
entered regardless of whether 10 Mb/s or 100 Mb/s
operation has been configured.
This bit will be set upon the assertion of the LPBK
pin, and will be automatically cleared upon its deas-
sertion.
13 Speed Selection Read/Write If auto-negotiation When bit 12 is clear, setting this bit configures the
is enabled via the CS8952T for 100 Mb/s operation. Clearing this bit
AN[1:0] pins, reset sets the configuration at 10 Mb/s. When bit 12 is set,
to 1; otherwise, this bit is ignored.
reset to 0
12 Auto-Neg Enable Read/Write If auto-negotiation Setting this bit enables the auto-negotiation process.
is enabled via the When this bit is set, bits 13 and 8 have no affect on
AN[1:0] pins, reset the link configuration. The link configuration is deter-
to 1; otherwise, mined by the auto-negotiation process. Clearing this
reset to 0
bit disables auto-negotiation.
11 Power Down
Read/Write 0
When this bit is set, the CS8952T enters a low power
consumption state. Clearing this bit allows normal
operation.
10 Isolate
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
Read/Write If PHYAD = 00000, Setting this bit causes the MII data path to be electri-
reset to 1; other- cally isolated by tri-stating all data outputs (i.e.
wise reset to the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL,
value on the ISO- and CRS). In addition the CS8952T will not respond
DEF pin
to the TXD[3:0], TX_EN, and TX_ER inputs. It will,
however, respond to MDIO and MDC. Clearing this
bit allows normal operation.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS206TPP2
31
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