T2080NXE8MQLB 查看數據表（PDF） - NXP Semiconductors.

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T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

3.7 RESET initialization

This section describes the AC electrical specifications for the RESET initialization timing

requirements. This table describes the AC electrical specifications for the RESET

initialization timing.

Table 19. RESET Initialization timing specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of PORESET_B

1

—

ms

1

Required input assertion time of HRESET_B

32

—

SYSCLKs 2, 3

Maximum rise/fall time of HRESET_B

—

10

SYSCLK

4

Maximum rise/fall time of PORESET_B

—

1

SYSCLK

4

PLL input setup time with stable SYSCLK before HRESET_B negation 100

—

μs

—

Input setup time for POR configs with respect to negation of

4

PORESET_B

—

SYSCLKs 2

Input hold time for all POR configs with respect to negation of

2

PORESET_B

—

SYSCLKs 2

Maximum valid-to-high impedance time for actively driven POR

—

5

configs with respect to negation of PORESET_B

SYSCLKs 2

Notes:

1. PORESET_B must be driven asserted before the core and platform power supplies are powered up.

2. SYSCLK is the primary clock input for the chip.

3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The

device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is

documented in section "Power-On Reset Sequence" in the chip reference manual.

4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

3.8 DDR3 and DDR3L SDRAM controller

This section describes the DC and AC electrical specifications for the DDR3 and DDR3L

SDRAM controller interface. Note that the required GVDD(typ) voltage is 1.5 V when

interfacing to DDR3 SDRAM and the GVDD(typ) voltage is 1.35 V when interfacing to

DDR3L SDRAM.

NOTE

When operating at a DDR data rate greater than or equal to

1866 MT/s, only one dual-ranked module per memory

controller is supported. DDR3L is not supported at a DDR data

rate of 2133 MT/s.

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

62

NXP Semiconductors

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