T2080NXE8MQLB 查看數據表（PDF） - NXP Semiconductors.

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T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

Table 40. IEEE 1588 AC timing specifications5 (continued)

Parameter/Condition

Symbol

Min

Typ

Max

Unit Notes

TSEC_1588_TRIG_IN1/2 pulse width

tT1588TRIGH

2 x tT1588CLK_MAX

—

—

Notes:

ns

3

1.TRX_CLK is the maximum clock period of ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip reference

manual for a description of TMR_CTRL registers.

2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference

manual for a description of TMR_CTRL registers.

3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For

example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns, respectively.

4. There are 3 input clock sources for 1588 i.e. TSEC_1588_CLK_IN, RTC and MAC clock / 2. When using

TSEC_1588_CLK_IN, the minimum clock period is 2 x tT1588CLK.

5. For recommended operating conditions, see Table 3.

This figure shows the data and command output AC timing diagram.

TSEC_1588_CLK_OUT

TSEC_1588_PULSE_OUT1/2

TSEC_1588_ALARM_OUT1/2

tT1588CLKOUT

tT1588CLKOUTH

tT1588OV

Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting.

Otherwise, it is counted starting at the falling edge.

Figure 17. IEEE 1588 output AC timing

This figure shows the data and command input AC timing diagram.

TSEC_1588_CLK_IN

tT1588CLK

tT1588CLKH

TSEC_1588_TRIG_IN1/2

tT1588TRIGH

Figure 18. IEEE 1588 input AC timing

3.12 USB interface

This section provides the AC and DC electrical specifications for the USB interface.

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

80

NXP Semiconductors

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