T2080NXE8MQLB 查看數據表（PDF） - NXP Semiconductors.

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T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

3.13.2 Integrated flash controller AC timing

This section describes the AC timing specifications for the integrated flash controller.

3.13.2.1 Test condition

This figure provides the AC test load for the integrated flash controller.

Output

Z0= 50 Ω

RL = 50 Ω

OVDD/2

Figure 19. Integrated flash controller AC test load

3.13.2.2 Integrated flash controller AC timing specifications

All output signal timings are relative to the falling edge of any IFC_CLK. The external

circuit must use the rising edge of the IFC_CLKs to latch the data.

All input timings are relative to the rising edge of IFC_CLKs.

This table describes the timing specifications of the integrated flash controller interface.

Table 45. Integrated flash controller timing specifications (OVDD = 1.8 V)5

Parameter

Symbol1

Min

Max

Unit

IFC_CLK cycle time

tIBK

10

-

ns

IFC_CLK duty cycle

tIBKH/ tIBK 45

55

%

IFC_CLK[n] skew to IFC_CLK[m]

tIBKSKEW

-

150

ps

Input setup

tIBIVKH

4

-

ns

Input hold

tIBIXKH

1

-

ns

Output delay

tIBKLOV

-

2.5

ns

Output hold

tIBKLOX

-2

-

ns

IFC_CLK to output high impedance for AD

tIBKLOZ

-

2

ns

1. All signals are measured from OVDD/2 of rising/falling edge of IFC_CLK to OVDD/2 of the signal in question.

2. Skew measured between different IFC_CLK signals at OVDD/2.

Notes

-

-

2

-

-

-

4

3

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

NXP Semiconductors

83

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