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ST72325S6B5(2007) 查看數據表(PDF) - STMicroelectronics

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ST72325S6B5 Datasheet PDF : 196 Pages
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16-BIT TIMER (Cont’d)
Figure 46. Counter Timing Diagram, Internal Clock Divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFD FFFE FFFF 0000 0001 0002 0003
TIMER OVERFLOW FLAG (TOF)
Figure 47. Counter Timing Diagram, Internal Clock Divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER FFFC
FFFD
0000
TIMER OVERFLOW FLAG (TOF)
0001
Figure 48. Counter Timing Diagram, Internal Clock Divided By 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
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