ST72325S6B5(2007) 查看數據表（PDF） - STMicroelectronics

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ST72325S6B5
(Rev.:2007)

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

STMicroelectronics 

16-BIT TIMER (Cont’d)

Notes:

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

3. In both internal and external clock modes,

OCFi and OCMPi are set while the counter

value equals the OCiR register value (see Fig-

ure 52 on page 81 for an example with fCPU/2

and Figure 53 on page 81 for an example with

fCPU/4). This behavior is the same in OPM or

PWM mode.

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit = 1). The OCFi bit is then

not set by hardware, and thus no interrupt request

is generated.

The FOLVLi bits have no effect in both One Pulse

mode and PWM mode.

Figure 51. Output Compare Block Diagram

16 BIT FREE RUNNING

COUNTER

16-bit

OUTPUT COMPARE

CIRCUIT

16-bit

16-bit

OC1R Register

OC2R Register

OC1E OC2E

OCIE

CC1 CC0

(Control Register 2) CR2

(Control Register 1) CR1

FOLV2 FOLV1 OLVL2

OLVL1

OCF1

OCF2 0

0

0

(Status Register) SR

Latch

1

Latch

2

OCMP1

Pin

OCMP2

Pin

80/196

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