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STM32WB35CEQ7ATR 查看數據表(PDF) - STMicroelectronics

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STM32WB35CEQ7ATR Datasheet PDF : 193 Pages
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Functional overview
STM32WB55xx STM32WB35xx
8. SRAM2a content is preserved when the bit RRS is set in PWR_CR3 register.
9. Stop 0 only. SMPS is automatically switched to Bypass or Open mode during Low power operation.
10. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
11. The HSE can be used by the RF subsystem according with the need to perform RF operation (Tx or Rx).
12. MSI maximum frequency.
13. In case RF will be used and HSE will fail.
14. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
15. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
16. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
17. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
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DS11929 Rev 10

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