PIC16C925T-S/CL View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16C925T-S/CL Datasheet PDF : 182 Pages
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PIC16C925/926
REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
WCOL
bit 7
R/W-0
SSPOV
R/W-0
SSPEN
R/W-0
CKP
R/W-0
SSPM3
R/W-0
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
WCOL: Write Collision Detect bit
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while SSPBUF is holding previous data. Data in SSPSR is lost on overflow.
Overflow only occurs in Slave mode. The user must read the SSPBUF, even if only transmitting data,
to avoid setting overflows. In Master mode, the overflow bit is not set since each operation is initiated
by writing to the SSPBUF register. (Must be cleared in software.)
0 = No overflow
In I2C mode:
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a “don’t care” in transmit
mode. (Must be cleared in software.)
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
When enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode:
When enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin (SS pin control enabled)
0101 = SPI Slave mode, clock = SCK pin (SS pin control disabled, SS can be used as I/O pin)
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1011 = I2C firmware controlled Master mode (slave idle)
1110 = I2C firmware controlled Master mode, 7-bit address with START and STOP bit interrupts enabled
1111 = I2C firmware controlled Master mode, 10-bit address with START and STOP bit interrupts enabled
1000, 1001, 1010, 1100, 1101 = reserved
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
x = Bit is unknown
DS39544A-page 60
Preliminary
2001 Microchip Technology Inc.
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