PIC16C925T-S/CL View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16C925T-S/CL Datasheet PDF : 182 Pages
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PIC16C925/926
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set for the Synchro-
nous Slave mode to be enabled. When the SS pin
is low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = ’1’, then the SS pin control must be
enabled.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 9-3:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
SDI (SMP = 1)
SSPIF
bit7
bit7
bit0
bit0
FIGURE 9-4:
SS (optional)
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SCK (CKP = 0)
SCK (CKP = 1)
SDO
SDI (SMP = 0)
SSPIF
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
bit0
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 63
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