PIC16C925/926
FIGURE 9-5:
SS
(not optional)
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SCK (CKP = 0)
SCK (CKP = 1)
SDO
SDI (SMP = 0)
SSPIF
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
bit0
TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address
Name Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
RESETS
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF
RBIF 0000 000x 0000 000u
0Ch
PIR1
LCDIF ADIF
—
— SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000
8Ch
PIE1
LCDIE ADIE
—
— SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h
TRISA
—
— PORTA Data Direction Control Register
87h
TRISC
—
— PORTC Data Direction Control Register
--11 1111 --11 1111
--11 1111 --11 1111
94h
SSPSTAT SMP CKE D/A
P
S
R/W
UA
BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
DS39544A-page 64
Preliminary
2001 Microchip Technology Inc.