ST72652 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72652

LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI

STMicroelectronics 

ST7265x

10 MISCELLANEOUS REGISTERS

MISCELLANEOUS REGISTER 1 (MISCR1)

Read /Write

Reset Value: 0000 0000 (00h)

7

0

IS11 IS10 MCO IS21 IS20 CP1 CP0 CPEN

Bits 7:6 = IS1[1:0] ei0 Interrupt sensitivity

Interrupt sensitivity, defined using the IS1[1:0] bits,

is applied to the ei0 interrupts (Port A):

IS11 IS10

00

01

10

11

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Bit 5 = MCO Main clock out selection

This bit enables the MCO alternate function on the

I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (fCPU output on

I/O port)

Bits 4:3 = IS2[1:0] ei1 Interrupt sensitivity

Interrupt sensitivity, defined using the IS2[1:0] bits,

is applied to the ei1 external interrupts (Port D):

IS21 IS20

00

01

10

11

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Bits 2:1 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is

applied in the different slow modes. Their action is

conditioned by the setting of the CPEN bit. These

two bits are set and cleared by software

Operating Mode

Stand-alone mode

(fOSC = 12 MHz)

USB mode

(48 MHz PLL)

fCPU

3 MHz

6 MHz*

1.5 MHz

750 KHz

375 KHz

6 MHz

8 MHz

2 MHz

1 MHz

250 KHz

CP1 CP0 CPEN

xx 0

00 1

10 1

01 1

11 1

xx 0

00 1

10 1

01 1

11 1

Caution:

– The ST7 core is not able to read or write in the

USB data buffer if the ST7265x is configured at 6

MHz in standalone mode.

– In USB mode, with fCPU ≤ 2 MHz, if the ST7 core

accesses the USB data buffer, this may prevent

the USB interface from accessing the buffer, re-

sulting in a USB buffer overrun error. This is be-

cause an access to memory lasts one cycle and

the USB has to send/receive at a fixed baud rate.

Bit 0 = CPEN Clock Prescaler Enable

This bit is set and cleared by software. It is used

with the CP[1:0] bits to configure the internal clock

frequency.

0: Default fCPU used (3 or 6 MHz)

1: fCPU determined by CP[1:0] bits

56/166

1

Share Link: