ST7265x
WATCHDOG TIMER (Cont’d)
11.1.8 Register Description
CONTROL REGISTER (CR)
Read /Write
Reset Value: 0111 1111 (7Fh)
7
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
0
dog option is enabled by option byte.
WDGA T6 T5 T4 T3 T2 T1 T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Table 18. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
T6
T5
T4
T3
T2
T1
T0
14
Reset Value
0
1
1
1
1
1
1
1
60/166
1