ST72652 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72652

LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI

STMicroelectronics 

ST7265x

11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

11.1.2 Main Features

s Programmable free-running downcounter (64

increments of 65536 CPU cycles)

s Programmable reset

s Reset (if watchdog activated) when the T6 bit

reaches zero

s Hardware Watchdog selectable by option byte

11.1.3 Functional Description

The counter value stored in the CR register (bits

T[6:0]), is decremented every 65,536 machine cy-

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T[6:0]) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. This downcounter is free-

running: it counts down even if the watchdog is

disabled. The value to be stored in the CR register

must be between FFh and C0h (see Table 17):

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

Table 17.Watchdog Timing (fCPU = 8 MHz)

CR Register

initial value

WDG timeout period

(ms)

Max

FFh

Min

C0h

524.288

8.192

Figure 37. Watchdog Block Diagram

RESET

WDGA T6

WATCHDOG CONTROL REGISTER (CR)

T5 T4 T3 T2 T1 T0

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER

÷65536

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