STPC® ATLAS
Figure 4-12. Asynchronous Write Cycle
HCLK
PA[ ] bus
CSx#
Tsetup
Tend
Thold
BE#[1:0]
t(s) PWR#
uc PD[15:0]
Prod PRDY
olete The Table 4-15. below refers to Vh, Va, Vs which and Hold time, as described in the Programming
s are the register value for Setup time, Active Time Manual.
Ob Table 4-15. Local Bus cycle lenght
- Cycle
t(s) Memory (FCSx#)
Peripheral (IOCSx#)
Tsetup
4 + Vh
4 + Vh
Tactive
2 + Va
2 + Va
Thold
4 + Vs
4 + Vs
Tend
4
4
Unit
HCLK
HCLK
duc Table 4-16. Local Bus Interface AC Timing
Obsolete Pro Name
Parameters
HCLK to PA bus
HCLK to PD bus
HCLK to FCS#[1:0]
HCLK to IOCS#[3:0]
HCLK to PWR#, PRD#
HCLK to BE#[1:0]
PD[15:0] Input setup to HCLK
Min
Max
Units
-
15
nS
-
15
nS
-
15
nS
-
15
nS
-
15
nS
-
15
nS
-
4
nS
PD[15:0] Input hold to HCLK
2
-
nS
PRDY Input setup to HCLK
-
4
nS
PRDY Input hold to HCLK
2
-
nS
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