STPCI2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

4.5.9 IDE INTERFACE

Figure 4-13, Figure 4-14 and Table 4-18 lists the

AC characteristics of the IDE interface.

Figure 4-13. IDE PIO timing diagram

CS#,DA[2:0]

DIOR#,DIOW#

Thold

Tsetup

DD[15:0]

) IORDY

uct(s Figure 4-14. IDE DMA timing diagram

te Prod CS#

sole REQ

- Ob ACK#

ct(s) DIOR#,DIOW#

rodu DD[15:0] read

Obsolete P DD[15:0] write

Thold

Tsetup

Table 4-18. IDE Interface Timing

Name

Tsetup

Thold

Parameters

DD[15:0] setup to PIOR#/SIOR# falling

DD[15:0} hold to PIOR#/SIOR# falling

Min

Max

Units

15

-

ns

0

-

ns

64/108

1

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