STPCC03 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCC03

PC Compatible Embeded Microprocessor

STMicroelectronics 

BOARD LAYOUT

Figure 6-11. Clock routing

Low skewclock driver:

L

DIMMCKn input

MCLKO

DIMMCKn input

DIMMCKn input

L+75mm*

STPCMCLKI

20pF

* No additionnal 75mm when SDRAM directly soldered on board

When using DIMM modules, schematics have to

be done carefully in order to avoid data busses

completely crossed on the board. This has to be

checked at the library level. In order to achive lay-

Figure 6-12. Optimum data bus layout for DIMM

out shown in Figure 6-12, schematics have to im-

plement the crossing described on Figure 6-13.

The DQM signals must be exchanged using the

same order.

MD[31:00]

STPC

SDRAMI/F

MD[63:32]

D[15:00]

D[47:32]

DIMM

D[31:16]

D[63:48]

Figure 6-13. Schematics for optimum data bus layout for DIMM

STPC

MD[15:00],DQM[1:0]

MD[31:16],DQM[3:2]

MD[47:32],DQM[5:4]

MD[63:48],DQM[7:6]

DIMM

D[15:00],DQM[1:0]

D[31:16],DQM[3:2]

D[47:32],DQM[5:4]

D[63:48],DQM[7:6]

45/51

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Share Link: