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CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
16.30 Sound Control Register (SCTL): Address 0xB1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 0001
XXXX
sclr
sdac
dss
clksel
This 4-bit register defines various control bits for the sound system.
Bit 3: sclr
This bit must always be programmed low.
Bit 2: sdac
This bit must be written as ‘0’.
Bit 1: dss
This bit selects Serial Sound mode.
Bit 0: clksel
This bit selects the clock used in the sound system. When this bit is
high, the internal CL-PS7500FE 32-MHz I/O reference clock is used;
when low the optional sound clock is used.
June 1997
ADVANCE DATA BOOK v2.0
THE VIDEO SOUND AND PROGRAMMER’S MODEL
155

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