CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

18. FLOATING-POINT COPROCESSOR PROGRAMMER’S MODEL

18.1 Overview

The ARM IEEE floating-point system has:

q 8 high-precision floating point registers, F0 to F7

q a working precision of 80 bits, comprising:

— 64-bit mantissa

— a 15-bit exponent

— a sign bit

18.1.1 Floating-Point Status Register

There is a floating-point status register (FPSR) which, like ARM's PSR, holds all the necessary status and

control information for the floating point system that an application should be able to access. It holds flags

which indicate various error conditions, such as overflow and division by zero. Each flag has a corre-

sponding trap enable bit that can be used to enable or disable a trap associated with the error condition.

Bits in the FPSR allow a client to distinguish different implementations of the floating-point system and to

enable or disable special features of the system.

18.1.2 Floating-Point Control Register

The FPA also contains a floating-point control register (FPCR). This is used to communicate status and

control information between the FPA and the FPA support code.

NOTE: The definition of the FPCR may be different for other implementations of the ARM IEEE floating point sys-

tem; the FPCR may not even exist in some implementations. Software outside the floating-point system

should therefore not use the FPCR directly.

18.2 Floating-Point Operation

All basic floating-point instructions operate as though the result were computed to infinite precision and

then rounded to the length and in the way specified by the instruction. The rounding is selectable from:

q Round to nearest

q Round to +infinity (P)

q Round to -infinity (M)

q Round to zero (Z)

The default is round to nearest: as required by the IEEE, this rounds to nearest even for the tie case. If

one of the other rounding modes is required it must be given in the instruction.

The floating-point system architecture is a load/store architecture (like the ARM CPU); the data-process-

ing operations only refer to floating-point registers. Values can be stored into ARM memory in one of five

formats (only four are visible at any one time since P and EP are mutually exclusive):

q IEEE Single Precision (S)

q IEEE Double Precision (D)

q IEEE Double Extended Precision (E)

160

FLOATING-POINT COPROCESSOR PROGRAMMER’S

MODEL

ADVANCE DATA BOOK v2.0

June 1997

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