CL-PS7500FE
System-on-a-Chip for Internet Appliance
q The value of d is arranged with the decimal point between d23 and d22, and is normalized so that for an ordi-
nary number 1 ≤ d23 ≤ 9.
q The guaranteed ranges for d and e are 21 and 4 digits respectively: e6, e5, e4 and d2, d1, d0 may always be
zero in a particular system.
q The result is undefined if any of the packed digits is hexadecimal A through F.
Expanded Packed Decimal Values
Table 18-4. Expanded Packed Decimal Values
Sign
Sign
Exponent Digit values
(top bit) (next bit)
Quiet NaN
x
x
FFFFFFF d23 > 7, rest non-zero
Signalling NaN x
x
FFFFFFF d23 < 8, rest non-zero
+/- Infinity
0,1
x
FFFFFFF all 0
+/- Zero
0,1
0
0000000 all 0
Number
0,1
0,1
0-9999999 1-9.99999999999999999999999
All other combinations are undefined.
18.4 The Floating-Point Status Register (FPSR)
The floating-point status register (FPSR) consists of:
q a system ID byte
q an exception trap enable byte
q a system control byte
q a cumulative exception flags byte
NOTE: The FPSR is not cleared on reset. It is typically cleared by the support code using an appropriate WFS.
18.4.1 System ID Byte
31
24
0
SysId
The 8-bit SysId allows a user or operating system to distinguish which floating-point system is in use. The
top bit (bit 31) is:
set
clear
for HARDWARE (i.e. fast) systems
for SOFTWARE (i.e. slow) systems
NOTE: The SysId is read-only.
164
FLOATING-POINT COPROCESSOR PROGRAMMER’S
MODEL
ADVANCE DATA BOOK v2.0
June 1997