CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Bit 10

Bit 11

Bit 12

SO - Select Synchronous Operation of FPA

If this bit is set, all floating-point instructions will execute synchronously and

ARM will be made to busy-wait until the instruction has completed. This will

allow precise exceptions to be reported but at the expense of increased

execution time. If this bit is clear, the class of floating-point instructions that can

execute asynchronously to ARM will do so. Exceptions that occur as a result of

these instructions may then be imprecise.

EP - Use Expanded Packed Decimal Format

If this bit is set, the expanded (four word) format will be used for Packed

Decimal numbers. Use of this expanded format allows conversion from

extended precision to packed decimal and back again to be carried out without

loss of accuracy. If this bit is clear, standard (three word) format is used for

Packed Decimal numbers.

AC - Use Alternative definition for C-flag on compare operations

If this bit is set, the ARM C-flag has the following interpretation after a compare:

C: Greater Than or Equal or Unordered

This interpretation of the C-flag allows more of the IEEE predicates to be

tested by means of single ARM conditional instructions than is possible using

the original interpretation of the C-flag as shown below.

If this bit is clear, the ARM C-flag has the following interpretation after a

compare:

C: Greater Than or Equal

Normally, reserved FPSR bits should not be altered by user code. However, they may be initialized to zero.

18.4.4 Cumulative Exception Flags Byte

31

7

54 3 2 1 0

Reserved IXC UFCOFCDZC IOC

Whenever an exception condition arises and the corresponding trap enable bit is not set, the appropriate

cumulative exception flag in bits 0–4 are set to ‘1’. If the relevant trap enable bit is set, an exception is

delivered to the user's program in a manner specific to the operating system.

NOTE: In the case of underflow, the state of the trap enable bit determines under which conditions the underflow

exception will arise.

These flags can only be cleared by a WFS instruction.

Normally, reserved FPSR bits should not be altered by user code. However, they may be initialized to zero.

IO -– Invalid Operation

The invalid operation exception arises when an operand is invalid for the operation to be performed. The

result (if the trap is not enabled) is a quiet NaN.

Invalid operations are:

q Any operation on a signalling NaN, except an LDF, LFM or SFM, or an MVF, MNF, ABS or STF without change

of precision.

q Magnitude subtraction of infinities, for example, + infinity + −infinity.

q Multiplication of 0 by an infinity.

166

FLOATING-POINT COPROCESSOR PROGRAMMER’S

MODEL

ADVANCE DATA BOOK v2.0

June 1997

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