CL-PS7500FE View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
q Packed Decimal (P)
q Expanded Packed Decimal (EP)
If it is required to preserve register contents exactly (including signalling NaNs), the LFM and SFM instruc-
tions should be used. Note however that LFM and SFM should only be used for register preservation
within programs and not for data which is to be transferred between programs and/or systems. The format
of data stored using SFM is implementation-dependent and can generally only be restored by an LFM
instruction from the same implementation.
Floating-point systems may be built from software only, hardware only, or some combination of software
and hardware and the results look the same to the programmer. However, the supervising operating sys-
tem needs to be aware the implementation in use to extract the best performance.
Similarly, compilers can be tuned to generate bunched FP instructions for the FPE and dispersed FP
instructions for the FPA to improve overall performance. The manner that exceptions are signalled is at
the discretion of the surrounding operating system.
NOTE: In the case of the FPA system, an exception caused by a floating-point data operation or a FLT may be asyn-
chronous (due to the nature of the ARM coprocessor interface.) Such an exception is raised some time after
the instruction has started, by which time the ARM may have executed a number of instructions following
the one that has failed. This means that the exact address of the instruction that caused the exception may
not be identifiable. However, all the information about the exception that the IEEE Standard recommends is
available.
Furthermore, in the FPA a fully synchronous, but slow mode of operation is available that allows the
address of the faulting instruction to be determined; this is described in bit 10 SO – Select Synchronous Oper-
ation of FPA on page 9-9.
18.3 ARM Integer and Floating-Point Number Formats
18.3.1 Integer
31
0
MSB
2’s complement
LSB
18.3.2 IEEE Single Precision (S)
31
30
23 22
0
sign
exponent
MSB
fraction
LSB
127
Normalized number exponent bias
126
Denormalized number exponent bias
18.3.3 IEEE Double Precision (D)
First
word
31
30
sign
exponent
20 19
MSB
fraction (ms part)
0
LSB
MSB
fraction (ls part)
LSB
1023
1022
Normalized number exponent bias
Denormalized number exponent bias
June 1997
ADVANCE DATA BOOK v2.0
FLOATING-POINT COPROCESSOR PROGRAMMER’S
MODEL
161
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