CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Single and Double Values

Table 18-1. Single and Double Values

Sign Exponent

Fraction

Value represented

Quiet NaN

x

Signalling NaN x

Infinity

sign

Zero

sign

Denormalized no sign

Normalized no. sign

maximum

1xxxxxxxxx IEEE Quiet NaN

maximum

0 non-zero IEEE Signalling NaN

maximum

0000000000 (-1)sign × infinity

0

0000000000 (-1)sign × 0

0

non-zero

(-1)sign × 0.fraction × 2-(denorm. bias)

not 0 and not maximum xxxxxxxxxx (-1)sign × 1.fraction × 2(exponent - norm. bias)

18.3.4 IEEE Extended Double Precision (E)

First

word

31

30

sign

zeros

15 14

fraction (ms part)

0

LSB

Second

word

J

MSB

fraction (ms part)

LSB

Third

word

MSB

fraction (ls part)

LSB

J

16383

is the bit to the left of the binary point

normalized and denormalized number exponent bias

Extended Values

Table 18-2. Extended Values

Sign Exponent

Quiet NaN

x

maximum

Signalling NaN

x

maximum

Infinity

sign

maximum

Zero

sign

0

Denormalized no sign

0

Normalized no. sign

not max

J Fraction

Value represented

x 1xxxxxxxxx IEEE Quiet NaN

x 0 non-zero IEEE Signalling NaN

0 0000000000 (-1)sign × infinity

0 0000000000 (-1)sign × 0

0 non-zero

(-1)sign × 0.fraction × 2-(denorm.bias)

1 xxxxxxxxxx

( - 1 )s i g n × 1 . f r a c t i o n × 2 ( ex p o n e n t -

norm.bias)

** Illegal value

** Illegal value

x not 0 and not max 0 xxxxxxxxxx

x

maximum

1 0000000000

NOTE: In general, illegal values must not be used, although specific floating-point implementations may use these

bit patterns for internal purposes.

162

FLOATING-POINT COPROCESSOR PROGRAMMER’S

MODEL

ADVANCE DATA BOOK v2.0

June 1997

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