CL-PS7500FE View Datasheet(PDF) - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
22.8 System Timing (Clocks)
Table 22-11. System Timing (Clocks)
Symbol Parameter
40 MHz
MIN
MAX
t cpck1l a
tcpck1ha
tmck1la
tmck1ha
tiock1la, b
tiock1ha, b
tcpck2l c
tcpck2hc
tmck2lc
tcpck2hc
tiock2lc, d
tiock2hc, d
CPUCLK low time
CPUCLK high time
MEMCLK low time
MEMCLK high time
I_OCLK low time
I_OCLK high time
CPUCLK low time
CPUCLK high time
MEMCLK low time
MEMCLK high time
I_OCLK low time
I_OCLK high time
11.25
11.25
7
7
14
14
6.25
6.25
5
5
7.8
7.8
tvckl
VCLKI low time
4
tvckh
VCLKI high time
4
thckl
HCLK low time
4
thckh
ted e
HCLK high time
ECLK to ED delay
4
5
7
tlcded
ECLK to ED delay (LCD mode)
tlcded ÷ 4 + 5 tlcded ÷ 4 + 7
a Divide-by-1 prescalar selected.
b I_OCLK = 32 MHz in Divide-by-1 mode.
c Divide-by-2 prescalar selected.
d I_OCLK = 64 MHz in Divide-by-2 mode.
e ECLK mark-space ratio is not always 1:1, depending on the pixel clock divide.
56 MHz
MIN
MAX
8
8
7
7
14
14
6.25
6.25
5
5
7.8
7.8
4
4
4
4
5
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
222
ELECTRICAL SPECIFICATIONS
ADVANCE DATA BOOK v2.0
June 1997
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