CL-PS7500FE View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
2.1 CL-PS7500FE Pin Descriptions (cont.)
Name
nCDACK
TC
nPCCS1
nPCCS2
LNBW
IORNW
nIOR
nIOW
CLK2
CLK8
REF8M
CLK16
Type
OCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OCZ
Drive
Strength
Description
1 NOT COMBO DACK: This is the chip select and DACK signal for a
PC Combo chip.
1 TERMINAL COUNT: This active-high signal is used in conjunction
with the nCDACK signal for pseudo DMA to a PC Combo chip.
1 This is the active-low chip select for an area of 16-MHz PC-type I/O
space.
1 This is the active-low chip select for an area of 16-MHz PC-type I/O
space.
2 LATCHED NOT BYTE WORD: This is a latched version of the inter-
nal NBW signal from the ARM processor, which transitions on the
falling edge of the internal MCLK signal.
2 I/O READ/NOT WRITE: This signal goes high during an I/O read,
and low during an I/O write.
2 NOT I/O READ: This signal has two functions:
1) It transitions low during simple and PC-type I/O reads; not used for
module-type I/O.
2) It is asserted low during ROM read cycles to act as an output
enable.
2 NOT I/O WRITE: This signal has two functions:
1) It transitions low during simple and PC-type I/O reads; not used for
module-type I/O.
2) It is asserted low during writes to ROM space, to act as a write
enable, if writes are enabled in the ROMCR register.
2 This is the 2-MHz I/O clock output.
2 This is the 8-MHz I/O clock output, the inverted version of REF8M.
2 This is the 8-MHz I/O clock output.
2 This is the 16-MHz I/O clock output, for PC-type I/O.
June 1997
ADVANCE DATA BOOK v2.0
21
PIN DESCRIPTIONS
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