ADV601LCJST View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV601LCJST Datasheet PDF : 44 Pages
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ADV601LC
(I) VCLK
tVCLK_CYC
(O) VCLKO
(VCLK2 = 0)
tVCLKO_D0
(I) VCLKO
(VCLK2 = 1)
NOTE:
tVCLKO_D1
USE VCLK FOR CLOCKING VIDEO-ENCODE OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS.
DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE.
Figure 19. Video Clock Timing
CCIR-656 Video Format Timing
The diagrams in this section show transfer timing for pixel (YCrCb), line (horizontal), and frame (vertical) data in CCIR-656 video
mode. All output values assume a maximum pin loading of 50 pF. Note that in timing diagrams for CCIR-656 video, the label CTRL
indicates the VSYNC, HSYNC, and FIELD pins.
Table XXI. CCIR-656 Video—Decode Pixel (YCrCb) Timing Parameters
Parameter
tVDATA_DC_D
tVDATA_DC_OH
tCTRL_DC_D
tCTRL_DC_OH
Description
VDATA Signals, Decode CCIR-656 Mode, Delay
VDATA Signals, Decode CCIR-656 Mode, Output Hold
CTRL Signals, Decode CCIR-656 Mode, Delay
CTRL Signals, Decode CCIR-656 Mode, Output Hold
Min
Max
N/A
14
4
N/A
N/A
11
5
N/A
Units
ns
ns
ns
ns
(O) VCLKO
(O) VDATA
(O) CTRL
VALID
t VDATA_DC_OH
VALID
t CTRL_DC_OH
t VDATA_DC_D
t CTRL_DC_D
VALID
VALID
Figure 20. CCIR-656 Video—Decode Pixel (YCrCb) Transfer Timing
VALID
VALID
Parameter
tVDATA_EC_S
tVDATA_EC_H
tCTRL_EC_D
tCTRL_EC_OH
(I) VCLK
Table XXII. CCIR-656 Video—Encode Pixel (YCrCb) Timing Parameters
Description
Min
VDATA Bus, Encode CCIR-656 Mode, Setup
2
VDATA Bus, Encode CCIR-656 Mode, Hold
5
CTRL Signals, Encode CCIR-656 Mode, Delay
N/A
CTRL Signals, Encode CCIR-656 Mode, Output Hold
20
Max
N/A
N/A
33
N/A
Units
ns
ns
ns
ns
(I) VDATA
(O) CTRL
VALID
ASSERTED
t CTRL_EC_OH
t CTRL_EC_D
VALID
t VDATA_EC_S
ASSERTED
t VDATA_EC_H
Figure 21. CCIR-656 Video—Encode Pixel (YCrCb) Transfer Timing
REV. 0
–33–
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