FDC37B80X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B80X

PC98/99 compliant enhanced super I/O controller with Keyboard / Mouse Wake-Up / 5 Volt Operation

SMSC -> Microchip 

CLOCKI

t1

t2

t2

FIGURE 7A - INPUT CLOCK TIMING

NAME

DESCRIPTION

t1 Clock Cycle Time for 14.318MHz (Note)

t2 Clock High Time/Low Time for 14.318MHz

Clock Rise Time/Fall Time (not shown)

MIN TYP

69.84

20

35

MAX

5

UNITS

ns

ns

ns

Note: Tolerance is ± 0.01%

t4

RESET_DRV

FIGURE 7B - RESET TIMING

NAME

DESCRIPTION

t4 RESET width (Note)

MIN TYP MAX UNITS

1.5

µs

Note: The RESET width is dependent upon the processor clock. The RESET must be active while

the clock is running and stable.

170

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