FDC37B80X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37B80X
SMSC -> Microchip
FDC37B80X Datasheet PDF : 194 Pages
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AEN
FDRQ,
PDRQ
nDACK
nIOR
or
nIOW
DATA
(DO-D7)
TC
t1
t14
t6
t5
t15
t16
t3
t2
t4
t12
t11
t8
t7
t13
t10
t9
DATA VALID
FIGURE 8A - DMA TIMING (SINGLE TRANSFER MODE)
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
DESCRIPTION
nDACK Delay Time from FDRQ High
DRQ Reset Delay from nIOR or nIOW
FDRQ Reset Delay from nDACK Low
nDACK Width
nIOR Delay from FDRQ High
nIOW Delay from FDRQ High
Data Access Time from nIOR Low
Data Set Up Time to nIOW High
Data to Float Delay from nIOR High
Data Hold Time from nIOW High
nDACK Set Up to nIOW/nIOR Low
nDACK Hold after nIOW/nIOR High
TC Pulse Width
AEN Set Up to nIOR/nIOW
AEN Hold from nDACK
TC Active to PDRQ Inactive
MIN
TYP
MAX
0
100
100
150
0
0
100
40
10
60
10
5
10
60
40
10
100
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
171
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