FDC37B80X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37B80X
SMSC -> Microchip
FDC37B80X Datasheet PDF : 194 Pages
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FIGURE 12B - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING
NAME
DESCRIPTION
t1 nIOW Asserted to PDATA Valid
t2 nWAIT Asserted to nWRITE Change (Note 1)
t3 nWRITE to Command Asserted
t4 nWAIT Deasserted to Command Deasserted
(Note 1)
t5 nWAIT Asserted to PDATA Invalid (Note 1)
t6 Time Out
t7 Command Deasserted to nWAIT Asserted
t8 SDATA Valid to nIOW Asserted
t9 nIOW Deasserted to DATA Invalid
t10 nIOW Asserted to IOCHRDY Asserted
t11 nWAIT Deasserted to IOCHRDY Deasserted
(Note 1)
t12 IOCHRDY Deasserted to nIOW Deasserted
t13 nIOW Asserted to nWRITE Asserted
t14 nWAIT Asserted to Command Asserted (Note 1)
t15 Command Asserted to nWAIT Deasserted
t16 PDATA Valid to Command Asserted
t17 Ax Valid to nIOW Asserted
t18 nIOW Asserted to Ax Invalid
t19 nIOW Deasserted to nIOW or nIOR Asserted
t20 nWAIT Asserted to nWRITE Asserted (Note 1)
t21 nWAIT Asserted to PDIR Low
t22 PDIR Low to nWRITE Asserted
MIN TYP MAX UNITS
0
50
ns
60
185
ns
5
35
ns
60
190
ns
0
ns
10
12
µs
0
ns
10
ns
0
ns
0
24
ns
60
160
ns
10
ns
0
70
ns
60
210
ns
0
10
µs
10
ns
40
ns
10
ns
40
ns
60
185
ns
0
ns
0
ns
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is
considered to have settled after it does not transition for a minimum of 50 nsec.
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