COM20022V-HT View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

COM20022V-HT

10Mbps ARCNET controller with 2Kx8 on-board RAM

SMSC -> Microchip 

The DMAEN bit (new to the COM20022) is located

at bit 3 of the ADDRESS PTR HIGH register. The

DMAEN bit is used to Disable/Enable the assertion

of the DMA Request (DREQ pin) after writing the

Address Pointer Low register. The SWAP bit (new

to the COM20022) is located at bit 0 of Address

Pointer Low register. The SWAP bit is used to

swap the upper and lower data byte. When 16 bit

access is enabled, (W16=1), A0 becomes the

SWAP bit.

Configuration Register

The Configuration Register is a read/write register

which is used to configure the different modes of

the COM20022. The Configuration Register

defaults to the value 0001 1000 upon hardware

reset only. SUBAD0 and SUBAD1 point to the

selection in Register 7.

Sub-Address Register

The sub-address register is new to the

COM20022, previously a reserved register. Bits 2,

1 and 0 are used to select one of the registers

assigned to address 7h. SUBAD1 and SUBAD0.

They are exactly same as those in the

Configuration register. If the SUBAD1 and

SUBAD0 bits in the Configuration register are

changed, the SUBAD1and SUBAD0 in the Sub-

Address register are also changed. SUBAD2 is a

new sub-address bit. It Is used to access the 3

new Set Up registers, SETUP2, BUS CONTROL

and DMA COUNT. These registers are selected

by setting SUBAD2=1. The SUBAD2 bit is

cleared automatically by writing the

Configuration register.

Write Bits[7:3] to ‘0’ for proper operation.

Setup 1 Register

The Setup 1 Register is a read/write 8-bit register

accessed when the Sub Address Bits

are set up accordingly (see the bit definitions of

the Configuration Register). The Setup 1 Register

allows the user to change the network speed

(data rate) or the arbitration speed independently,

invoke the Receive All feature and change the

nPULSE1 driver type. The data rate may be

slowed to 156.25Kbps and/or the arbitration

speed may be slowed by a factor of two. The

Setup 1 Register defaults to the value 0000 0000

upon hardware reset only.

Setup 2 Register

The Setup 2 Register is new to the COM20022.

It is an 8-bit read/write register accessed when

the Sub Address Bits SUBAD[2:0] are set up

accordingly (see the bit definitions of the Sub

Address Register). This register contains bits for

various functions. The CKUP1,0 bits select the

clock to be generated from the 20 MHz crystal.

The RBUSTMG bit is used to Disable/Enable

Fast Read function for High Speed CPU bus

support. The EF bit is used to enable the new

timing for certain functions in the COM20022 (if

EF = 0, the timing is the same as in the

COM20020 Rev. B). See Appendix “A”. The

NOSYNC bit is used to enable the NOSYNC

function during initialization. If this bit is reset,

the line has to be idle for the RAM initialization

sequence to be written. If set, the line does not

have to be idle for the initialization sequence to

be written. See Appendix “A”.

The RCNTM[1,0] bits are used to set the time-

out period of the recon timer. Programming this

timer for shorter time periods has the benefit of

shortened network reconfiguration periods. The

time periods shown in the table on the following

page are limited by a maximum number of

nodes in the network. These time-out period

values are for 10Mbps. For other data rates,

scale the time-out period time values

accordingly; the maximum node count remains

the same.

33

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