COM20022V-HT View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
COM20022V-HT Datasheet PDF : 88 Pages
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BIT
BIT NAME
7 Reset
6 Command
Chaining Enable
5 Transmit Enable
4,3 Extended
Timeout 1,2
2 Backplane
Table 10 - Configuration Register
SYMBOL
DESCRIPTION
RESET
A software reset of the COM20022 is executed by writing a
logic "1" to this bit. A software reset does not reset the
microcontroller interface mode, nor does it affect the
Configuration Register. The only registers that the software
reset affect are the Status Register, the Next ID Register,
and the Diagnostic Status Register. This bit must be
brought back to logic "0" to release the reset.
CCHEN
This bit, if high, enables the Command Chaining operation
of the device. Please refer to the Command Chaining
section for further details. A low level on this bit ensures
software compatibility with previous SMSC ARCNET
devices.
TXEN
When low, this bit disables transmissions by keeping
nPULSE1, nPULSE2 if in non-Backplane Mode, and
nTXEN pin inactive. When high, it enables the above
signals to be activated during transmissions. This bit
defaults low upon reset. This bit is typically enabled once
the Node ID is determined, and never disabled during
normal operation. Please refer to the Improved Diagnostics
section for details on evaluating network activity.
ET1, ET2
These bits allow the network to operate over longer
distances than the default maximum 1 mile by controlling
the Response, Idle, and Reconfiguration Times. All nodes
should be configured with the same timeout values for
proper network operation. For the COM20022 with a 20
MHz crystal oscillator, the bit combinations follow:
Reconfig
Response Idle Time Time
ET2
ET1 Time ( S) ( S)
(mS)
0
0
298.4
328
420
0
1
149.2
164
420
1
0
74.7
82
420
1
1
18.7
20.5
210
Note: These values are for 10Mbps and RCNTMR[1,0]=00.
Reconfiguration time is changed by the RCNTMR1 and
RCNTMR0 bits.
BACK-
PLANE
A logic "1" on this bit puts the device into Backplane Mode
signaling which is used for Open Drain and Differential
Driver interfaces.
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