COM20022V-HT View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
COM20022V-HT Datasheet PDF : 88 Pages
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BIT
BIT NAME
2 No Synchronous
1,0 Reconfiguration
Timer 1, 0
BIT
BIT NAME
7 16 Bit Access
6 Reserved
5 Internal Terminal
Counter Enable;
Re-Trigger mode
Table 12 - Setup 2 Register
SYMBOL
DESCRIPTION
NOSYNC This bit is used to enable the SYNC command during
initialization. NOSYNC= 0, Enable (Default) The line must
be idle for the RAM initialization sequence to be written.
NOSYNC= 1, Disable:) The line does not have to be idle for
the RAM initialization sequence to be written. See appendix
“A”.
RCNTM1,0 These bits are used to program the reconfiguration timer as a
function of maximum node count. These bits set the time out
period of the reconfiguration timer as shown below. The
time out periods shown are for 10 Mbps.
RCNTM1 RCNTM0
Time Out
Max Node Count
Period
0
0
210 mS
Up to 255 nodes
0
1
52.5 mS
Up to 64 nodes
1
0
26.25 mS
Up to 32 nodes
1
1
13.125 mS*
Up to 16 nodes
Note*: The node ID value 255 must exist in the network for
13.125 mS timeout to be valid.
Table 13 – Bus Control Register
SYMBOL
DESCRIPTION
W16
This bit is used to Disable/Enable the 16 bit access. It
influences both CPU cycle and DMA cycle. W16= 0:
Disable (Default); W16= 1: Enable
This bit is undefined.
ITCEN/
RTRG
The function of this bit is mode dependent. ITCEN is for
Non-Burst or Burst mode. RTRG is for the two
Programmable-Burst modes.
ITCEN = 0: Terminate the DMA only by External TC. ITCEN
= 1: Terminate the DMA by Internal or External TC.
RTRG = 0: External Re-Trigger mode; Negated DREQ pin is
Re-asserted by falling edge of nREFEX pin. RTRG = 1:
Internal Re-Trigger mode; Negated DREQ pin is Re-
asserted by timeout of internal gate timer (350ns/750ns).
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