COM20022V-HT View Datasheet(PDF) - SMSC -> Microchip
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COM20022V-HT Datasheet PDF : 88 Pages
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Table 15 - DMA Timing
PARAMETER
MIN TYP
t1 nDACK Inactive Pulse Width
t2 The First DREQ Assertion Delay After Writing Low 4 Tarb 5
Pointer
Tarb
t3 DREQ Assert Delay from nREFEX Active at
0
Programmable Burst Transfer Mode
t4 DREQ Assertion Delay from Write/Read Inactive at
0
Non-Burst Transfer Mode
t5 DREQ Assertion Delay from nDACK
Inactive due to Timeout of Gate Timer at
Programmable Burst Transfer Mode
GTTM
bit =0
GTTM
bit=1
7Txtl
15Txtl
t6 DREQ Negation Delay from Write/Read Active
0
t7 DREQ Negation Delay from TC and Write/Read
0
Active
t8 Data Access Time from Read Active
t9 Data Float Delay from Read Inactive
0
t10 nREFEX Active Pulse Width
20
t11 Write Active Pulse Width
CASE 20
1W
CASE 65
2W
t12 Read Active Pulse Width
CASE 60
1R
CASE 100
2R
t13 Active Pulse Overlap Width between TC and
20
Write/Read
t14 Write/Read Inactive Pulse Width
CASE1w/1R 20
CASE2w/2R 30
t15 Write Cycle Interval Period
4Tarb
t16 Read Cycle Interval Period
CASE1R
CASE2R
t17 Data Setup to Write Inactive
t18 Data Hold From Write Inactive
t19 nCS High Setup to nDACK Active
t20 nCS High Hold from nDACK Inactive
t21 DREQ Active Setup to nDACK Active
t22 DIR Setup to nDS Low (Motorola mode only)
t23 DIR Hold from nDS High (Motorola mode only)
t24 nDACK Setup to Write/Read Active
t25 nDACK Hold After Write/Read Inactive
t26 nREFEX Inactive Time
4Tarb
4Tarb+
30nS
30
10
20
20
20
10
10
30
5
3Txtl
MAX
30
5Tarb
+40ns
40
40
8Txtl
+40ns
16Txtl
+40ns
40
40
40
20
UNIT
ns
NOTE
Note 1
ns Note 3
ns Note 4
Note 2
ns Note 4
ns Note 4
ns Note 4
ns Note 4
ns
ns Note
4,5
ns
ns Note
4,5
ns
ns Note 4
ns Note
ns
4,5
Note
1,4
Note
1,4,5
ns Note 4
ns Note 4
ns
ns
ns
ns
ns
ns Note 4
ns Note 4
Note 2
Note 1: Tarb is the ARBITRATION CLOCK PERIOD. It depends on Topr and SLOWARB bit.
SLOWARB must set to “1” if the data rate is over 5 Mbps. (i.e. 10 Mbps)
79
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