STV0672-chipsetf-3-1.fm
Pinout and pin descriptions
Name
SRAMVSS
VDDIO
VSSCORE
VSSIO
SRAMVSS
VDDCORE/
REG3V31
VID3V3
AUD3V3
VBLOOM2
VBLTW3
VBG
VCMTCAS
VRT4
VDDHI
VBASE
VBUS
AIN
AOUTP
AOUTN
PORB
D[4]
D[3]
D[2]
D[1]
D[0]
QCK
CLKIN
LST/D[5]
Pin Number Type
Description
21
GND In-column SRAM analog ground.
43
PWR Digital pad ring power.
29
GND Digital logic ground.
30
GND Digital pad ring ground.
21
GND In-column SRAM analogue ground.
45
PWR Digital logic power/Regulated 3V3 digital supply
12
PWR On-chip Video Supply Voltage Regulator Output
3
PWR On-chip Audio Amplifier Voltage Regulator Output
ANALOG SIGNALS
8
OA
Anti-blooming pixel reset voltage
7
OA
Bitline test white level reference
1
OA
Internally generated bandgap reference voltage 1.22V
13
IA
Common-mode input for column pre-amp.
2
IA
Pixel reset voltage (nominally a monitor point but can be overdriven
externally)
9
OA
Output from voltage doubler, 4.6V -> 4.8V
46
OA
Drive for base of external bipolar
47
IA
Incoming power supply 3.3V-> 6V
4
IA
Analog input to Audio Amplifier
5
OA
Analog output of Audio Amplifier (positive)
6
OA
Analog output of Audio Amplifier (negative)
16
OA
Power-on Reset (Bar) Output.
DIGITAL VIDEO INTERFACE
36
ODT Tri-stateable 5-wire output data bus.
35
- D[4] is the most significant bit.
34
- D[4:0] have programmable drive strengths 2, 4 and 6 mA
33
32
42
ODT Tri-stateable data qualification clock.
40
BI↑
LVDS negative Clock input
37
ODT Tri-stateable Line start output
May be configured as tri-stateable output data bit 5 D[5].
26/41
29 November 2000
Commercial in confidence