Customer Datasheet, Rev 3.1, 29 November 2000
STV0672-chipsetf-3-1.fm
Name Pin Number Type
Description
FST/D[6]
D[7]
OEB
38
ODT Tri-stateable Frame start signal.
May be configured as tri-stateable output data bit 6 D[6].
41
ODT Tri-stateable Data wire (ms data bit).
May be configured as tri-stateable output data bit 6 D[6].
20
ID↓
Digital output (tri-state) enable.
DIGITAL CONTROL SIGNALS
RESETB
SUSPEND
31
ID↑
System Reset. Active Low.
May be configured as System Sync. Active Low.
15
ID↑
USB Suspend Mode Control signal. Active High
If this feature is not required then the support circuit must pull the pin to
ground. The combination of an active high signal and pull up pad was
chosen to limit current drawn by the device while in suspend mode.
SERIAL INTERFACE
SCL
SDA
18
BI↑
Serial bus clock (input only).
17
BI↑
Serial bus data (bidirectional, open drain).
SYSTEM CLOCKS
CLKI/CLKIP
39
ID↓
Schmitt Buffered Clock input or LVDS positive Clock input
CLKIN
40
ID↓
LVDS negative Clock input
1. Pre production samples of this device had Reg3V3 and VDDCORE bonded out separately. The production version
of the device will have Reg3V3 and VDDCORE common bonded out to pin 45. There will be no requirement to
change ANY support design/PCB’s as the two signals from pin 44 and pin 45 were connected together on the ref-
erence design.
2. Vbloom pin was bonded on pre-production samples but will not be bonded on production parts
3. VBLTW pin was bonded on pre-production samples but will not be bonded on production parts
4. VRT pin was bonded on pre-production samples but will not be bonded on production parts
Key
A
OA
BI
BI↑
BI↓
Analog Input
Analog Output
Bidirectional
Bidirectional with internal pull-up
Bidirectional with internal pull-down
D
ID↑
ID↓
OD
ODT
Digital Input
Digital input with internal pull-up
Digital input with internal pull-down
Digital Output
Tri-stateable Digital Output
29 November 2000
Commercial in confidence
27/41