AD1816AJS View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD1816AJS Datasheet PDF : 52 Pages
| |||
AD1816A
Table I. DSP Port Time Slot Map
Time Slot SDI Pin
SDO Pin
0
Control Word Input
Status Word Output
1
Control Register Data Input
Control Register Data Output
2
* SS/SB ADC Right Input (to ISA)
SS/SB ADC Right Output (from Codec)
3
* SS/SB ADC Left Input (to ISA)
SS/SB ADC Left Output (from Codec)
4
* SS/SB DAC Right Input (to Codec) SS/SB DAC Right Output (from ISA)
5
* SS/SB DAC Left Input (to Codec) SS/SB DAC Left Output (from ISA)
6
* FM DAC Right Input (to Codec)
FM DAC Right Output (from FM Synth Block)
7
* FM DAC Left Input (to Codec)
FM DAC Left Output (from FM Synth Block)
8
* I2S (1) DAC Right Input (to Codec) I2S (1) DAC Right Output (from I2S Port (1))
9
* I2S (1) DAC Left Input (to Codec) I2S (1) DAC Left Output (from I2S Port (1))
10
* I2S (0) DAC Right Input (to Codec) I2S (0) DAC Right Output (from I2S Port (0))
11
* I2S (0) DAC Left Input (to Codec) I2S (0) DAC Left Output (from I2S Port (0))
*This data is ignored by the AD1816A unless the channel pair is in intercept mode (see below).
SS = Sound System Mode
SB = SoundBlaster Mode
At start-up (after pin reset), there are exactly 12 time slots per frame. The frame rate will be 57,291 and 2/3 Hz (11 MHz sclk/
[16 bits × 12 slots]). Interfacing with an Analog Devices 21xx family DSP can be achieved by putting the ADSP-21xx in 24 slot per
frame mode, where the first 12 and second 12 slots in the ADSP-21xx frame are identical.
The frame rate can be changed from its default by a write to the DFS(2:0) bits in register 33. Rate choices are: Maximum (57,291
and 2/3 Hz default), SS capture rate, SS playback rate, FM rate, I2S Port (1) rate, or I2S Port (0) rate. When the frame rate is less
than 57,261 and 2/3 Hz, extra SCLK periods are added to fill up the time. The number of SCLK periods added will vary somewhat
from frame to frame.
To control the sample data flow of each channel through the DSP Port, valid input, valid output and request bits are located in the
control and status words. If the specified channel sample rate is equal to the frame rate, these bits may be ignored since they will
always be set to “1.â€
By default, the DSP serial port allows only codec sample data I/O to be monitored. Intercept modes must be enabled to make substi-
tutions in sample data flow to and from the codec. There are five bits in SS register 33, which enable intercept mode for SS capture,
SS playback, FM playback, I2S Port (1) playback and I2S Port (0) playback.
Control Word Input (Slot 0 SDI)
15
14
FCLR
RES
7
6
ALIVE
R/W
13
12
11
10
9
8
RES
SSCVI
SSPVI
FMVI
IS1VI
IS0VI
5
4
3
2
1
0
IA[5:0]
IA [5:0]
R/W
ALIVE
IS0VI
IS1VI
FMVI
Indirect Register Address. Sound System Indirect Register Address defines the address of indirect registers shown
in Table VI.
Read/Write request. Either a read from or a write to an SS indirect register occurs every frame. Setting this bit ini-
tiates an SS indirect register read while clearing this bit initiates an SS indirect register write.
DSP port alive bit. When set, this bit indicates to the power-down timer that the DSP port is active. When cleared,
this bit indicates that the DSP port is inactive.
I2S Port 0 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for the I2S
port 0 channel pair, or (2) The AD1816A did not request data from the I2S port 0 channel pair in the previous
frame. Otherwise, setting this bit indicates that slots 10 and 11 contain valid right and left I2S Port 0 substitution
data. When this bit is cleared, data in slots 10 and 11 is ignored.
I2S Port 1 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for I2S port
1 channel pair or (2) The AD1816A did not request data from the I2S port channel pair in the previous frame.
Otherwise, setting this bit indicates that Slots 8 and 9 contain valid right and left I2S Port 1 substitution data.
When this bit is cleared, data in slots 8 and 9 is ignored.
FM Synthesis Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for the
FM synthesis channel pair or (2) The AD1816A did not request data from the FM synthesis channel pair in the
previous frame (see the FMRQ Bit 9 in the status word output). Otherwise, setting this bit to 1 indicates that slots
6 and 7 contain valid right and left FM synthesis channel substitution data. When this bit is reset to 0, data in slots
6 and 7 is ignored.
–18–
REV. A
Share Link: 